library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;
    
entity ADDR2MUX_logic is
    port(ADDR2MUX: in bit_vector(1 downto 0);
         PCoffset11: in unsigned(15 downto 0);
         PCoffset9: in unsigned(15 downto 0);
         PCoffset8: in unsigned(15 downto 0);
         LSHF1: in bit;
         ADDR2MUX_out: out unsigned(15 downto 0));
     end entity ADDR2MUX_logic;
     
architecture build of ADDR2MUX_logic is
    signal temp: unsigned(15 downto 0);
    begin
        ADDR2MUX_out <= temp sll 1 when LSHF1 = '1'
        else
            temp;
        process(ADDR2MUX,PCoffset11,PCoffset8)
            begin
                if ADDR2MUX = "00" then
                    temp <= "0000000000000000";
                elsif ADDR2MUX = "01" then
                    temp <= PCoffset9;
                elsif ADDR2MUX = "10" then
                    temp <= PCoffset8;
                elsif ADDR2MUX = "11" then
                    temp <= PCoffset11;
                end if;
                --if LSHF1 = '1' then
                --    temp <= temp sll 1;
                --end if;
        end process;
    end build;